1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a photodiode, and to a method of forming a buried layer for blocking or eliminating slow photo-generated carriers in a region where the electric field is low.
2. Description of the Related Art
The absorption length of 850 nm light in silicon is 15–20 μm, which is much longer than the 1–2 μm absorption lengths of typical III–V semiconductors such as GaAs at this wavelength.
As a result, high speed silicon photodetectors are often designed with a lateral structure, rather than a vertical structure, in an attempt to decouple the photocarrier transit time from the absorption length and to minimize the complexity of fabricating large scale vertical features, since semiconductor processing is typically optimized for thin film (<<1 micron) features.
These lateral structures typically take the form of either: (1) a PIN detector with diffused or implanted fingers; or (2) a metal-semiconductor-metal (MSM) detector. In these lateral structures, the electric field is relatively high at the surface of the semiconductor and decreases at lower depths. Photocarriers that are generated relatively deep below the surface of the semiconductor experience a weak electric field and slowly drift up to the contacts. These “slow carriers” create a low frequency tail in the frequency response that limits the overall bandwidth of the device to be less than about 1 GHz in silicon.
Thus, in a photodetector employing silicon, the absorption length is somewhat large (e.g., it could extend to 20 μm below the surface (or even more depending upon the wavelength)) and, as a result, if absorption is too deep, the “slow carriers” will still reach the contact areas (e.g., the anode and cathode) of the detector. A problem arises in that an electric field which is induced deep in the semiconductor is not as strong as that near the surface at the anode and cathode.
Thus, again, the carriers will slowly drift upward to the anode and cathode. Hence, when a very short pulse of light is exciting the detector, in an ideal photodetector, the same (e.g., shape, etc.) would be reflected in the current that the photodetector produces since the very short pulse of light would result in a very short pulse of electrons in the detector.
However, if the carriers are collected over a long period of time, then instead of a short current pulse, one would obtain a fast rise in the current followed by a slow decay (e.g., a long “tail”), since it takes some time to collect the deep (slow) carriers. This is a problem in that the “long tail” is unacceptable for transfer of information and the like, especially over an optical fiber. Specifically, since each pulse is used for transmitting one bit, then the bits must be spaced fairly far away from each other on a timing scale. Otherwise, it would be difficult to distinguish one bit from another if the long tail was present. This limits the bit rate that can be used with this photodetector.
The above effect can be somewhat minimized by using a lateral trench detector (LTD) structure, as described in U.S. Pat. No. 6,177,289 to J. Crow, et al., entitled “Lateral trench optical detector”, and U.S. Pat. No. 6,451,702, to M. Yang, et al., entitled “Methods for forming lateral trench optical detectors”. However, the carriers generated below the deep trenches limit the bandwidth, as described in M. Yang, et al., Proceedings of the 59th DRC, p. 153, (2001).
Even GaAs MSM detectors, where most of the absorption occurs near the surface, have bandwidths limited to about 2–3 GHz due to the fringing electric field. As a result, the majority of photodetectors currently used in industry utilize vertical PIN structures to achieve 10 GHz bandwidth operation.
The objective is to block the slow carriers without degrading other properties of the detector. One solution is to block the carriers with a silicon-on-insulator (SOI) structure, as described in commonly assigned, copending U.S. patent application Ser. No. 09/678,315, to Y. H. Kwark et. al, entitled “Silicon-on-insulator trench photodiode structure for improved speed and differential isolation”, J. Y. L. Ho, et. al., Appl. Phys. Lett. 69, 16 Yang, et. al., 2001 paper 24-1 (2001). Bandwidths of about 2.0 GHz at 3.3 V with a peak quantum efficiency of 51% have been reported using SOI, as described in Min Yang, et. al., 2001 paper 24-1 (2001).
However, if the SOI layer is present, then a very different material is provided beneath the silicon layer which performs the absorption. That is, some of the light which has not been absorbed will reach the barrier layer, and then will be reflected back into the detector. This is not necessarily disadvantageous, but if the surface is very flat (e.g., the buried oxide is extremely flat), then the surface acts as a specular reflector, and, as a result, the structure's reflectivity will be highly dependent upon the wavelength. Hence, this structure acts as a resonant cavity formed by the three layers (e.g., an upper layer, the silicon layer, and the buried oxide layer).
Thus, the reflection at the bottom silicon/oxide interface creates a resonant cavity structure in which the quantum efficiency is a strong function of the wavelength of the incident light. This effect is also referred to as the “etalon effect.” While the SOI film is at least 8 μm thick to allow sufficient light absorption, its thickness must be controlled with an accuracy of better than 0.75% to achieve a minimum reflection. Such tight control is difficult to obtain over a single wafer and from wafer-to-wafer.
Specifically, the characteristics of the resonator include that there are minimas in the transmission. Each of the minima represents that almost no light is being absorbed in the detector. The minima should be avoided if possible, but this is difficult to achieve if the photodetector structure layer is thick, since then the minima are very closely spaced. On the other hand, while it may be possible to make the layer thinner, then there would not be a large absorption volume and the quantum efficiency would suffer (e.g., the amount of photons which are converted into electrons is very poor).
Moreover, the use of SOI has other disadvantages. For example, the cost of a SOI wafer is currently about five times that of bulk silicon.
Further, SOI wafer fabrication techniques such as SIMOX or bonding are suited for making thin SOI wafers, having a SOI thickness of less than about 1 μm thick. As a result, the fabrication of thick SOI wafers requires an additional step of silicon epitaxy for thickening the SOI film to about 8 μm.
In another conventional technique, as described in U.S. Pat. No. 5,525,828, to Bassous et al., entitled “High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields”, such a problem of light generating carriers existing deep within the semiconductor beyond the influence of the electric field, have been addressed.
Specifically, U.S. Pat. No. 5,525,828 has attempted to form a barrier layer at a predetermined distance below an interface for limiting collection of light generated carriers by an electrode.
However, as a barrier for the slow carriers, U.S. Pat. No. 5,525,828 proposes a heavily doped layer. The heavily doped layer has a short lifetime for minority carriers, thus increasing the chance of recombination for slow carriers that were formed below the heavily doped layer.
Further, such a heavily doped layer is difficult to manufacture due to dopant diffusion problems. Indeed, while it is disclosed that the heavily doped layer reduces the carriers lifetime, there is nothing disclosed about the formation of a potential barrier to block the carriers. A lightly doped P-N junction would circumvent problems such as dopant diffusion and mutual-capacitance that are typical with heavily doped layers.